Metal oxide semiconductor device and method of fabricating the same

ABSTRACT

A method of fabricating an MOS device is provided. First, gates and source/drain regions of transistors are formed on a substrate. A photodiode doped region and a floating node doped region are formed in the substrate. Thereafter, a spacer stacked layer including a bottom layer, an inter-layer and a top layer is formed to cover each gate of the transistors. Afterwards, a first mask layer having an opening exposing at least the photodiode doped region is formed on the substrate, and then the top layer exposed by the opening is removed. Next, the first mask layer is removed, and then a second mask layer is formed on a region correspondingly exposed by the opening. A portion of the top layer and the inter-layer exposed by the second mask layer is removed to form spacers on sidewalls of the gates.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an integrated circuit and a method offabricating the same, and more particularly to a metal oxidesemiconductor (MOS) device and a method of fabricating the same.

2. Description of Related Art

The process of forming a complementary metal oxide semiconductor (CMOS)image sensor is compatible to the process of forming a CMOS transistor.Consequently, the CMOS image sensor can be fabricated with otherperipheral circuits on a same chip. Thus, the power consumption and thecosts of fabricating the image sensors are significantly reduced. In therecent years, the CMOS image sensor has replaced a charge-coupled device(CCD) in the low-end application and become more and more predominant.

The CMOS image sensor includes a photodiode and a plurality oftransistors. The photodiode is constructed by a P-N junction constitutedof an N-doped region and a P-substrate. The transistors are N-type MOStransistors having N-type gates (N-poly NMOSs). Currently, the CMOSimage sensor includes a 3-transistor (3-T) configuration and a4-transistor (4-T) configuration.

A typical 3-T configuration refers to the CMOS image sensor including areset transistor, a source follower transistor, a select transistor, anda photodiode. However, the 3-T configuration brings about high darkcurrent, increases readout noises and adversely affects the imagequality, thus reducing the performance of the devices. Hence, the 4-Tconfiguration is implemented more frequently.

FIG. 1 schematically illustrates a conventional 4-T CMOS image sensor.

In FIG. 1, the CMOS image sensor includes a substrate 100, a transfertransistor 102 disposed on the substrate 100, a reset transistor 104, asource follower transistor 106, a select transistor 108, a photodiode110 disposed in the substrate 100, a floating node 112 disposed in thesubstrate 100, and a P-well 114 disposed in the substrate 100. Since the4-T CMOS image sensor includes the transfer transistor 102, the highdark current of the 3-T CMOS image sensor can be avoided.

In the 4-T CMOS image sensor, the spacer material deposited on thephotodiode region is frequently kept, so as to protect the photodioderegion from being damaged during the etching and the formation of thespacers and to avoid the dark current from increasing. Generally, thethickness of the spacers exceeds 1000 angstrom, and the spacers areoften made of silicon nitride. Thereby, excessive silicon nitride isleft in the photodiode region, which blocks lights emitting into thephotodiode region and impairs the sensitivity of the sensor. On thecontrary, if the spacers are made of silicon oxide, a subsequentlyformed anti-reflective layer is disposed far away from the photodioderegion due to the excessive thickness of silicon oxide. Hence, thereflection cannot be effectively suppressed.

SUMMARY OF THE INVENTION

The present invention is directed to an MOS device and a method offabricating the same, protecting a photodiode region from being damagedduring the etching and the formation of spacers and further avoiding adark current from increasing.

The present invention is directed to an MOS device and a method offabricating the same. Thereby, the sensitivity of a CMOS image sensorcan be enhanced.

The present invention is directed to an MOS device and a method offabricating the same, which can effectively prevent reflectivity.

The present invention provides a method of fabricating an MOS device.The method includes first providing a substrate including a CMOS imagesensor region and a non-CMOS image sensor region. A plurality of gatesand source/drain regions of transistors are then formed on thesubstrate, and a photodiode doped region and a floating node dopedregion are formed in the CMOS image sensor region. Next, a spacerstacked layer covering the gate of each of the transistors is formed onthe substrate. The spacer stacked layer at least includes a bottomlayer, an inter-layer, and a top layer from bottom to top. Thereafter, afirst mask layer is formed on the substrate. The first mask layer has anopening which exposes at least the photodiode doped region and isextended to a part of the transistor adjacent to the photodiode dopedregion. Afterwards, a removing process is performed to remove the toplayer exposed by the opening. The first mask layer is removed. A secondmask layer is then formed on a region correspondingly exposed by theopening. After that, a portion of the top layer and the inter-layerexposed by the second mask layer is removed to form a spacer on asidewall of each of the transistors. Next, the second mask layer isremoved. Thereafter, a salicide block (SAB) layer is formed on thesubstrate, and a portion of the top layer, the inter-layer, and thebottom layer is removed with use of the SAB layer as an etching mask soas to expose a plurality of predetermined regions. Finally, a metalsilicide layer is formed on each of the predetermined regions.

According to one embodiment of the present invention, the materials ofthe bottom layer/the inter-layer/the top layer include siliconoxide/silicon nitride/silicon oxide.

According to one embodiment of the present invention, the thicknesses ofsilicon oxide/silicon nitride/silicon oxide are 300-500 angstrom/100-300angstrom/300-700 angstrom.

According to one embodiment of the present invention, the removingprocess further includes removing the inter-layer disposed below theopening.

According to one embodiment of the present invention, the materials ofthe bottom layer/the inter-layer/the top layer include siliconoxide/silicon nitride/silicon oxide.

According to one embodiment of the present invention, the thicknesses ofsilicon oxide/silicon nitride/silicon oxide are 100-300 angstrom/100-300angstrom/300-700 angstrom.

According to one embodiment of the present invention, the openingexposes the photodiode doped region, the floating node doped region, thetransistor adjacent to the photodiode doped region, and a part of thetransistor adjacent to the floating node doped region.

According to one embodiment of the present invention, the removingprocess further includes removing the inter-layer disposed below theopening.

According to one embodiment of the present invention, the openingexposes the whole CMOS image sensor region.

According to one embodiment of the present invention, the removingprocess further includes removing the inter-layer disposed below theopening.

According to one embodiment of the present invention, the first masklayer includes a patterned photoresist layer.

According to one embodiment of the present invention, the second masklayer includes a patterned photoresist layer.

According to one embodiment of the present invention, the material ofthe SAB layer is selected from one of the groups consisting of siliconnitride, SiON, silicon oxide and a combination thereof.

The present invention further provides an MOS device disposed on asubstrate including a CMOS image sensor region and a non-CMOS imagesensor region. The MOS device includes a CMOS image sensor disposed inthe CMOS image sensor region and a second transistor disposed in thenon-CMOS image sensor region. The CMOS image sensor includes aphotodiode doped region, a plurality of first transistors, at least abottom layer, an SAB layer, and a floating node doped region. Thephotodiode doped region is disposed in the substrate. The firsttransistors disposed on the substrate include a transfer transistor, areset transistor, a source follower transistor and a select transistor.The transfer transistor is adjacent to the photodiode doped region, andat least a sidewall of a gate of the transfer transistor adjacent to thephotodiode doped region has no spacers. The floating node doped regionis disposed in the substrate between the transfer transistor and thereset transistor. The bottom layer covers a surface of the transistorshaving no spacers, a surface of the photodiode doped region, and asurface of the floating node doped region. The SAB layer covers thebottom layer.

According to one embodiment of the present invention, the MOS devicefurther includes an inter-layer at least disposed between the SAB layerand the bottom layer over the photodiode doped region.

According to one embodiment of the present invention, the material ofthe inter-layer is different from the material of the bottom layer.

According to one embodiment of the present invention, the spacers atrespective sidewalls of at least one of the first transistors aredifferently shaped.

According to one embodiment of the present invention, said firsttransistor having the differently-shaped spacers at the respectivesidewalls is the reset transistor.

According to one embodiment of the present invention, the MOS devicefurther includes a liner layer disposed between the spacers and thefirst transistors. The spacers include an outer spacer and an innerspacer.

According to one embodiment of the present invention, the material ofthe outer spacers includes silicon oxide, while the material of theinner spacers includes silicon nitride.

According to one embodiment of the present invention, the inter-layer isdisposed between the bottom layer and the SAB layer over the photodiodedoped region, the transfer transistor, the floating node doped regionand a part of the reset transistor.

According to one embodiment of the present invention, the spacers of thefirst transistors and the spacer of the second transistor are equallyshaped.

According to one embodiment of the present invention, the spacer on asidewall of at least one of the first transistors and the spacer of thesecond transistor are differently shaped.

According to one embodiment of the present invention, both sidewalls ofthe gate of the transfer transistor and a sidewall of the gate of thereset transistor adjacent to the transfer transistor comprise nospacers.

According to one embodiment of the present invention, the spacer of atleast one of the first transistors and a spacer of the second transistorare differently shaped.

According to one embodiment of the present invention, the spacers at therespective sidewalls of at least one of the first transistors aredifferently shaped.

According to one embodiment of the present invention, said firsttransistor having the differently-shaped spacers at the respectivesidewalls is the reset transistor.

According to one embodiment of the present invention, the MOS devicefurther includes a liner layer disposed between the spacers of the firsttransistors and the gates. The spacers include an outer spacer and aninner spacer.

According to one embodiment of the present invention, the material ofthe outer spacers includes silicon oxide, while the material of theinner spacers includes silicon nitride.

According to one embodiment of the present invention, the spacers of thefirst transistors and the spacer of the second transistor are equallyshaped.

According to one embodiment of the present invention, the spacers of thefirst transistors and the spacer of the second transistor aredouble-layered spacers, respectively.

According to one embodiment of the present invention, both sidewalls ofthe gate of the transfer transistor and a sidewall of the gate of thereset transistor adjacent to the transfer transistor include no spacers.

According to one embodiment of the present invention, all of the firsttransistors have no spacers.

According to one embodiment of the present invention, the MOS devicefurther includes a liner layer disposed on each of the sidewalls of thegates of the first transistors.

According to one embodiment of the present invention, the material ofthe bottom layer includes silicon oxide.

The MOS device and the method of fabricating the same disclosed in thepresent invention can prevent the photodiode region from being damagedduring the etching and the formation of the spacers and further avoidthe dark current from increasing.

The MOS device and the method of fabricating the same disclosed in thepresent invention are able to enhance the sensitivity of the CMOS imagesensor.

The MOS device and the method of fabricating the same disclosed in thepresent invention are capable of effectively suppressing the reflection.

In order to the make the aforementioned and other objects, features andadvantages of the present invention comprehensible, several embodimentsaccompanied with figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates a conventional 4-T CMOS image sensor.

FIGS. 2A through 2D are cross-sectional flow charts schematicallyillustrating a process of fabricating of an MOS device according to anembodiment of the present invention.

FIGS. 3A through 3D are cross-sectional flow charts schematicallyillustrating a process of fabricating of an MOS device according toanother embodiment of the present invention.

FIGS. 4A through 4D are cross-sectional flow charts schematicallyillustrating a process of fabricating of an MOS device according tostill another embodiment of the present invention.

FIGS. 5A through 5D are cross-sectional flow charts schematicallyillustrating a process of fabricating of an MOS device according to yetstill another embodiment of the present invention.

FIGS. 6A through 6D are cross-sectional flow charts schematicallyillustrating a process of fabricating of an MOS device according to yetstill another embodiment of the present invention.

FIGS. 7A through 7D are cross-sectional flow charts schematicallyillustrating a process of fabricating of an MOS device according toanother embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS First Embodiment

FIGS. 2A through 2D are cross-sectional flow charts schematicallyillustrating a process of fabricating of an MOS device according to anembodiment of the present invention.

Referring to FIG. 2A, a substrate 200 is provided. The substrate 200 is,for example, a semiconductor substrate such as a silicon substrate.First, an isolation structure 202 is formed in the substrate 200 todefine active regions 204 and 206. The active region 204 is a CMOS imagesensor region, and the active region 206 is a non-CMOS image sensorregion. The isolation structure 202 is formed by performing a shallowtrench isolation method or a localized oxidation isolation method. Then,a P-type filed region (not shown) is formed at the periphery and on thebottom of the isolation structure 202.

Next, a transfer resistor 212, a reset transistor 214, a source followertransistor 216, a select transistor 218, a floating node doped region224, and a photodiode doped region 226 are formed in the CMOS imagesensor region 204 of the substrate 200. In addition, a transistor 220 isformed in the non-CMOS image sensor region 206. The transfer resistor212, the reset transistor 214, the source follower transistor 216, theselect transistor 218 and the transistor 220 all include gate dielectriclayers 208, gates 210, and source/drain extension regions 222. Thematerial of the gate dielectric layers 208 is, for example, siliconoxide, and the method of forming the gate dielectric layers 208 includesperforming a thermal oxidation process, for example. The material of thegates 210 is polysilicon, for example, and the method of forming thegates 210 includes performing a chemical vapor deposition (CVD) process,for example. The source/drain extension regions 222 may be constructedby performing ion implantation processes.

Thereafter, a spacer stacked layer 228 is formed on the substrate 200.The spacer stacked layer 228 includes a bottom layer 230, an inter-layer232 and a top layer 234. The etching rate of the inter-layer 232 isdifferent from that of the bottom layer 230 and the top layer 234. Inone embodiment, the materials of the bottom layer 230/the inter-layer232/the top layer 234 include silicon oxide/silicon nitride/siliconoxide, for example, and the thicknesses thereof are 300-500angstrom/100-300 angstrom/300-700 angstrom. The method of forming thebottom layer 230/the inter-layer 232/the top layer 234 includesperforming the CVD process, for example.

Thereafter, referring to FIG. 2B, a mask layer 136 is formed on the toplayer 234. The mask layer 136 has an opening 137 which exposes thephotodiode doped region 226 and is extended to a part of the gate 208 ofthe transfer transistor 212 adjacent to the photodiode doped region 226.The mask layer 136 is, for example, a patterned photoresist layer, andthe method of forming the mask layer 136 includes coating photoresist,performing an exposure process, and implementing a development process.

After that, the top layer 234 exposed by the opening 137 is removed withuse of the mask layer 136 as a hard mask, such that the inter-layer 232below the top layer 234 is exposed. The method of removing the top layer234 may be a dry etching method or a wet etching method. In oneembodiment, the materials of the bottom layer 230/the inter-layer232/the top layer 234 include silicon oxide/silicon nitride/siliconoxide. The remained inter-layer 232 may be employed as ananti-reflective layer. And the stress arisen from the remainedinter-layer 232 may be cushioned through the bottom layer 230 in thethickness of 300-500 angstrom.

Afterwards, referring to FIG. 2C, the mask layer 136 is removed. Anothermask layer 138 is then formed on a region correspondingly exposed by theopening 137, such that the photodiode doped region 226 and a part of thegate 208 of the transfer transistor 212 are covered while other regionsare exposed. The mask layer 138 is, for example, a patterned photoresistlayer, and the method of forming the mask layer 138 includes coatingphotoresist, performing the exposure process, and implementing thedevelopment process.

Next, an anisotropic etching operation is performed with use of the masklayer 138 as the mask to remove a portion of the top layer 234 and theinter-layer 232 exposed by the mask layer 138, such that spacers 240 areformed at a sidewall of the transfer transistor 212 and at bothsidewalls of the reset transistor 214, the source follower transistor216, the select transistor 218, and the transistor 220. Each of thespacers 240 is constructed by an inner spacer 232 a formed by theinter-layer 232 and an outer spacer 234 a formed by the top layer 234.The anisotropic etching operation is a plasma etching process, forexample. During the etching process, the photodiode doped region 226 iscovered by the mask layer 138, and thus the photodiode doped region 226is not damaged.

Thereafter, as shown in FIG. 2D, the mask layer 138 is removed. Afterthat, the ion implantation process may be performed to form source/draincontact regions 223 in the substrate 200. The source/drain contactregions 223 and the source/drain extension regions 222 together formsource/drain regions 225. Afterwards, an salicide block (SAB) layer 242is formed on the substrate 200, and the bottom layer 230 exposed by theSAB layer 242 is etched and removed, such that predetermined regions inwhich a metal silicide layer to be formed are exposed. The material ofthe SAB layer 242 is, for example, silicon nitride, SiON, or siliconoxide, and the method of forming the SAB layer 242 includes performingthe CVD process or a high-temperature oxidation (HTO) process, forexample. In one embodiment, the SAB layer 242 covers the photodiodedoped region 226, the transfer transistor 212, the floating node dopedregion 224, and a part of the gate 210 of the reset transistor 214.During the etching process, the spacers 240 of the transfer transistor212 and of the reset transistor 214 both covered by the SAB layer 242are left. And the spacers 240 of the reset transistor 214, of the sourcefollower transistor 216, of the select transistor 218 and of thetransistor 220 all exposed by the SAB layer 242 are partially etched toform spacers 240 a composed of inner spacers 232 b and outer spacers 234b. A liner layer 230 a sandwiched between one of the spacers 240 a andthe gates 210 is left after the bottom layer 230 is etched. Next, asalicid process is performed to form a metal silicide layer 244 on thegates 210 and on the source/drain regions 225 both exposed by the SABlayer 242. The metal silicide layer 244 is formed by, for example,forming a metal layer on the substrate 200 at first. The metal used forfabricating the metal layer may be a refractory metal selected from oneof the groups consisting of nickel, cobalt, titanium, copper,molybdenum, tantalum, tungsten, erbium, zirconium, platinum and an alloyincluding one or more of said metals. Afterwards, an annealing processis performed to enable the silicon in the substrate 200 or in the gates210 to react with the metal layer and to form a metal silicide having alower resistance. Thereafter, the unreacted metal layer is removed.

Thereafter, the successive processes are performed. Since the subsequentprocesses are well known to people skilled in the art, detaileddescriptions are omitted herein.

In the above fabrication process, a passivation layer (not shown) may bealternatively formed on a surface of the photodiode doped region 226 soas to prevent current leakage. The passivation layer is, for example, aP-doped region.

Second Embodiment

FIGS. 3A through 3D are cross-sectional flow charts schematicallyillustrating a process of fabricating of another MOS device according toan embodiment of the present invention.

Referring to FIG. 3A, a substrate 200 is provided. The substrate 200 is,for example, a semiconductor substrate such as a silicon substrate.First, an isolation structure 202 is formed in the substrate 200 todefine active regions 204 and 206. The active region 204 is a CMOS imagesensor region, and the active region 206 is a non-CMOS image sensorregion. The isolation structure 202 is formed by performing a shallowtrench isolation method or a localized oxidation isolation method. Then,a P-type filed region (not shown) is formed at the periphery and on thebottom of the isolation structure 202.

Next, a transfer resistor 212, a reset transistor 214, a source followertransistor 216, a select transistor 218, a floating node doped region224, and a photodiode doped region 226 are formed in the CMOS imagesensor region 204 of the substrate 200. In addition, a transistor 220 isformed in the non-CMOS image sensor region 206. The transfer resistor212, the reset transistor 214, the source follower transistor 216, theselect transistor 218 and the transistor 220 all include gate dielectriclayers 208, gates 210, and source/drain extension regions 222. Thematerial of the gate dielectric layers 208 is, for example, siliconoxide, and the method of forming the gate dielectric layers 208 includesperforming a thermal oxidation process, for example. The material of thegates 210 is polysilicon, for example, and the method of forming thegates 210 includes performing a CVD process, for example. Thesource/drain extension regions 222 may be constructed by performing ionimplantation processes.

Thereafter, a spacer stacked layer 228 is formed on the substrate 200.The spacer stacked layer 228 includes a bottom layer 230, an inter-layer232 and a top layer 234. The etching rate of the inter-layer 232 isdifferent from that of the bottom layer 230 and the top layer 234. Inone embodiment, the materials of the bottom layer 230/the inter-layer232/the top layer 234 include silicon oxide/silicon nitride/siliconoxide, for example, and the thicknesses thereof are 300-500angstrom/100-300 angstrom/300-700 angstrom. The method of forming thebottom layer 230/the inter-layer 232/the top layer 234 includesperforming the CVD process, for example.

After that, referring to FIG. 3B, a mask layer 236 is formed on the toplayer 234. The mask layer 236 has an opening 237 which exposes thephotodiode doped region 226 and is extended to the transfer transistor212 adjacent to the photodiode doped region 226, the floating node dopedregion 224, and a part of the gate 208 of the reset transistor 214. Themask layer 236 is, for example, a patterned photoresist layer, and themethod of forming the mask layer 236 includes coating photoresist,performing an exposure process, and implementing a development process.

After that, the top layer 234 exposed by the opening 237 is removed withuse of the mask layer 236 as a hard mask, such that the inter-layer 232below the top layer 234 is exposed. The method of removing the top layer234 may be a dry etching method or a wet etching method. In oneembodiment, the materials of the bottom layer 230/the inter-layer232/the top layer 234 include silicon oxide/silicon nitride/siliconoxide. The remained inter-layer 232 may be employed as ananti-reflective layer. And the stress arisen from the remainedinter-layer 232 may be cushioned through the bottom layer 230 in thethickness of 300-500 angstrom.

Afterwards, referring to FIG. 3C, the mask layer 236 is removed. Anothermask layer 238 is then formed on a region correspondingly exposed by theopening 237, such that the photodiode doped region 226, the transfertransistor 212, the floating node doped region 224 and a part of thegate 208 of the reset transistor 214 are covered while other regions areexposed. The mask layer 238 is, for example, a patterned photoresistlayer, and the method of forming the mask layer 238 includes coatingphotoresist, performing the exposure process, and implementing thedevelopment process.

Next, an anisotropic etching operation is performed with use of the masklayer 238 as the mask to remove a portion of the top layer 234 and theinter-layer 232 exposed by the mask layer 238, such that spacers 240 areformed at a sidewall of the reset transistor 214 and at both sidewallsof the source follower transistor 216, the select transistor 218, andthe transistor 220. Each of the spacers 240 is constructed by an innerspacer 232 a formed by the inter-layer 232 and an outer spacer 234 aformed by the top layer 234. The anisotropic etching operation is aplasma etching process, for example. During the etching process, thephotodiode doped region 226 is covered by the mask layer 238, and thusthe photodiode doped region 226 is not damaged.

Thereafter, as shown in FIG. 3D, the mask layer 238 is removed. Afterthat, the ion implantation process may be performed to form source/draincontact regions 223 in the substrate 200. The source/drain contactregions 223 and the source/drain extension regions 222 together formsource/drain regions 225. Afterwards, an SAB layer 242 is formed on thesubstrate 200, and the bottom layer 230 exposed by the SAB layer 242 isetched and removed, such that predetermined regions in which a metalsilicide layer to be formed are exposed. The material of the SAB layer242 is, for example, silicon nitride, SiON, or silicon oxide, and themethod of forming the SAB layer 242 includes performing the CVD processor an HTO process, for example. In one embodiment, the SAB layer 242covers the photodiode doped region 226, the transfer transistor 212, thefloating node doped region 224, and a part of the gate 210 of the resettransistor 214. During the etching process, the inter-layer 232 and thebottom layer 230 respectively disposed on the transfer transistor 212and on the reset transistor 214 both covered by the SAB layer 242 areleft. And the spacers 240 of the reset transistor 214, of the sourcefollower transistor 216, of the select transistor 218 and of thetransistor 220 all exposed by the SAB layer 242 are partially etched toform spacers 240 a composed of inner spacers 232 b and outer spacers 234b. A liner layer 230 a sandwiched between one of the spacers 240 a andthe gates 210 is left after the bottom layer 230 is etched. Next, asalicid process is performed to form a metal silicide layer 244 on thegates 210 and on the source/drain regions 225 both exposed by the SABlayer 242. The metal silicide layer 244 is formed by, for example,forming a metal layer on the substrate 200 at first. The metal used forfabricating the metal layer may be a refractory metal selected from oneof the groups consisting of nickel, cobalt, titanium, copper,molybdenum, tantalum, tungsten, erbium, zirconium, platinum and an alloyincluding one or more of said metals. Afterwards, an annealing processis performed to enable the silicon in the substrate 200 or in the gates210 to react with the metal layer and to form a metal silicide having alower resistance. Thereafter, the unreacted metal layer is removed.

Thereafter, the successive processes are performed. Since the subsequentprocesses are well-known to people skilled in the art, detaileddescriptions are omitted herein.

In the above fabrication process, a passivation layer (not shown) may bealternatively formed on a surface of the photodiode doped region 226 soas to prevent current leakage. The passivation layer is, for example, aP-doped region.

Third Embodiment

FIGS. 4A through 4D are cross-sectional flow charts schematicallyillustrating a process of fabricating of another MOS device according toan embodiment of the present invention.

Referring to FIG. 4A, a substrate 200 is provided. The substrate 200 is,for example, a semiconductor substrate such as a silicon substrate.First, an isolation structure 202 is formed in the substrate 200 todefine active regions 204 and 206. The active region 204 is a CMOS imagesensor region, and the active region 206 is a non-CMOS image sensorregion. The isolation structure 202 is formed by performing a shallowtrench isolation method or a localized oxidation isolation method. Then,a P-type field region (not shown) is formed at the periphery and on thebottom of the isolation structure 202.

Next, a transfer resistor 212, a reset transistor 214, a source followertransistor 216, a select transistor 218, a floating node doped region224, and a photodiode doped region 226 are formed in the CMOS imagesensor region 204 of the substrate 200. In addition, a transistor 220 isformed in the non-CMOS image sensor region 206. The transfer resistor212, the reset transistor 214, the source follower transistor 216, theselect transistor 218 and the transistor 220 all include gate dielectriclayers 208, gates 210, and source/drain extension regions 222. Thematerial of the gate dielectric layers 208 is, for example, siliconoxide, and the method of forming the gate dielectric layers 208 includesperforming a thermal oxidation process, for example. The material of thegates 210 is polysilicon, for example, and the method of forming thegates 210 includes performing a CVD process, for example. Thesource/drain extension regions 222 may be constructed by performing ionimplantation processes.

Thereafter, a spacer stacked layer 228 is formed on the substrate 200.The spacer stacked layer 228 includes a bottom layer 230, an inter-layer232 and a top layer 234. The etching rate of the inter-layer 232 isdifferent from that of the bottom layer 230 and the top layer 234. Inone embodiment, the materials of the bottom layer 230/the inter-layer232/the top layer 234 include silicon oxide/silicon nitride/siliconoxide, for example, and the thicknesses thereof are 300-500angstrom/100-300 angstrom/300-700 angstrom. The method of forming thebottom layer 230/the inter-layer 232/the top layer 234 includesperforming the CVD process, for example.

After that, referring to FIG. 4B, a mask layer 336 is formed on the toplayer 234. The mask layer 336 has an opening 337 exposing the whole CMOSimage sensor region 204. The mask layer 336 is, for example, a patternedphotoresist layer, and the method of forming the mask layer 336 includescoating photoresist, performing an exposure process, and implementing adevelopment process.

After that, the top layer 234 exposed by the opening 337 is removed withuse of the mask layer 336 as a hard mask, such that the inter-layer 232below the top layer 234 is exposed. The method of removing the top layer234 may be a dry etching method or a wet etching method. In oneembodiment, the materials of the bottom layer 230/the inter-layer232/the top layer 234 include silicon oxide/silicon nitride/siliconoxide. The remained inter-layer 232 may be employed as ananti-reflective layer. And the stress arisen from the remainedinter-layer 232 may be cushioned through the bottom layer 230 in thethickness of 300-500 angstrom.

Afterwards, referring to FIG. 4C, the mask layer 336 is removed. Anothermask layer 338 is then formed on a region correspondingly exposed by theopening 337, such that the whole CMOS image sensor region 204 is coveredwhile other regions are exposed. The mask layer 338 is, for example, apatterned photoresist layer, and the method of forming the mask layer338 includes coating photoresist, performing the exposure process, andimplementing the development process.

Next, an anisotropic etching operation is performed with use of the masklayer 338 as the mask to remove a portion of the top layer 234 and theinter-layer 232 exposed by the mask layer 338, such that spacer 240 isformed at a sidewall of the transistor 220. the spacers 240 isconstructed by an inner spacer 232 a formed by the inter-layer 232 andan outer spacer 234 a formed by the top layer 234. The anisotropicetching operation is a plasma etching process, for example. During theetching process, the photodiode doped region 226 is covered by the masklayer 338, and thus the photodiode doped region 226 is not damagedthrough etching.

Thereafter, as shown in FIG. 4D, the mask layer 338 is removed. Afterthat, the ion implantation process may be performed to form source/draincontact regions 223 in the substrate 200. The source/drain contactregions 223 and the source/drain extension regions 222 together formsource/drain regions 225. Afterwards, an SAB layer 242 is formed on thesubstrate 200, and the bottom layer 230 exposed by the SAB layer 242 isetched and removed, such that predetermined regions in which a metalsilicide layer to be formed are exposed. The material of the SAB layer242 is, for example, silicon nitride, SiON, or silicon oxide, and themethod of forming the SAB layer 242 includes performing the CVD processor an HTO process, for example. In one embodiment, the SAB layer 242covers the photodiode doped region 226, the transfer transistor 212, thefloating node doped region 224, and a part of the gate 210 of the resettransistor 214. During the etching process, the inter-layer 232 and thebottom layer 230 respectively disposed on the transfer transistor 212and on the reset transistor 214 both covered by the SAB layer 242 areleft. The inter-layer 232 and the bottom layer 230 on the resettransistor 214, the source follower transistor 216, and the selecttransistor 218 exposed by the SAB layer 242 together construct spacers240 a and liner layers 230 a. And the spacers 240 of the transistor 220are partially etched to form spacers 240 a composed of inner spacers 232b and outer spacers 234 b. The liner layer 230 a sandwiched between oneof the spacers 240 a and the gates 210 are left after the bottom layer230 is etched. Next, a salicid process is performed to form a metalsilicide layer 244 on the gates 210 and on the source/drain regions 225both exposed by the SAB layer 242. The metal silicide layer 244 isformed by, for example, forming a metal layer on the substrate 200 atfirst. The metal used for fabricating the metal layer may be arefractory metal selected from one of the groups consisting of nickel,cobalt, titanium, copper, molybdenum, tantalum, tungsten, erbium,zirconium, platinum and an alloy including one or more of said metals.Afterwards, an annealing process is performed to enable the silicon inthe substrate 200 or in the gates 210 to react with the metal layer andto form a metal silicide having a lower resistance. Thereafter, theunreacted metal layer is removed.

Thereafter, the successive processes are performed. Since the subsequentprocesses are well-known to people skilled in the art, detaileddescriptions are omitted herein.

In the above fabrication process, a passivation layer (not shown) may bealternatively formed on a surface of the photodiode doped region 226 soas to prevent current leakage. The passivation layer is, for example, aP-doped region.

In the above three embodiments, as shown in FIGS. 2B, 3B and 4B, the toplayer 234 exposed by the openings 137, 237 and 337 of the mask layers136, 236 and 336 is removed, and the bottom layer 230 and theinter-layer 232 are left on the photodiode doped region 226, whichenables the inter-layer 232 to be an anti-reflective layer and allowsthe bottom layer 230 to be a buffer layer. Alternatively, the bottomlayer 230 can be the only layer left on the photodiode doped region 226.The required anti-reflective layer on the photodiode doped region 226can be formed later in the subsequent processes. It is not necessary forthe bottom layer 230 to cushion the stress arisen from the remainedinter-layer 232, for the inter-layer 232 on the photodiode doped region226 is removed. Hence, the bottom layer 230 in the present embodimentcan be in a thinner thickness than the bottom layer 230 provided in theabove-mentioned three embodiments. Detailed descriptions will be givenhereinafter with reference to FIGS. 5A through 5D, FIGS. 6A through 6D,and FIGS. 7A through 7D.

Fourth Embodiment

FIGS. 5A through 5D are cross-sectional flow charts schematicallyillustrating a process of fabricating of an MOS device according to anembodiment of the present invention.

Referring to FIG. 5A, a substrate 200 is provided. The substrate 200 is,for example, a semiconductor substrate such as a silicon substrate.First, an isolation structure 202 is formed in the substrate 200 todefine active regions 204 and 206. The active region 204 is a CMOS imagesensor region, and the active region 206 is a non-CMOS image sensorregion. The isolation structure 202 is formed by performing a shallowtrench isolation method or a localized oxidation isolation method. Then,a P-type field region (not shown) is formed at the periphery and on thebottom of the isolation structure 202.

Next, a transfer resistor 212, a reset transistor 214, a source followertransistor 216, a select transistor 218, a floating node doped region224, and a photodiode doped region 226 are formed in the CMOS imagesensor region 204 of the substrate 200. In addition, a transistor 220 isformed in the non-CMOS image sensor region 206. The transfer resistor212, the reset transistor 214, the source follower transistor 216, theselect transistor 218 and the transistor 220 all include gate dielectriclayers 208, gates 210, and source/drain extension regions 222. Thematerial of the gate dielectric layers 208 is, for example, siliconoxide, and the method of forming the gate dielectric layers 208 includesperforming a thermal oxidation process, for example. The material of thegates 210 is polysilicon, for example, and the method of forming thegates 210 includes performing a CVD process, for example. Thesource/drain extension regions 222 may be constructed by performing ionimplantation processes.

Thereafter, a spacer stacked layer 228 is formed on the substrate 200.The spacer stacked layer 228 includes a bottom layer 230, an inter-layer232 and a top layer 234. The etching rate of the inter-layer 232 isdifferent from that of the bottom layer 230 and the top layer 234. Inone embodiment, the materials of the bottom layer 230/the inter-layer232/the top layer 234 include silicon oxide/silicon nitride/siliconoxide, for example, and the thicknesses thereof are 100-300angstrom/100-300 angstrom/300-700 angstrom. The method of forming thebottom layer 230/the inter-layer 232/the top layer 234 includesperforming the CVD process, for example.

Thereafter, referring to FIG. 5B, a mask layer 136 is formed on the toplayer 234. The mask layer 136 has an opening 137 which exposes thephotodiode doped region 226 and is extended to a part of the gate 208 ofthe transfer transistor 212 adjacent to the photodiode doped region 226.The mask layer 136 is, for example, a patterned photoresist layer, andthe method of forming the mask layer 136 includes coating photoresist,performing an exposure process, and implementing a development process.

After that, the top layer 234 and the inter-layer 232 both exposed bythe opening 137 are removed with use of the mask layer 136 as a hardmask, such that the bottom layer 230 below the inter-layer 232 isexposed. The method of removing the top layer 234 and the inter-layer232 may be a dry etching method or a wet etching method.

Afterwards, referring to FIG. 5C, the mask layer 136 is removed. Anothermask layer 138 is then formed on a region correspondingly exposed by theopening 137, such that the photodiode doped region 226 and a part of thegate 208 of the transfer transistor 212 are covered while other regionsare exposed. The mask layer 138 is, for example, a patterned photoresistlayer, and the method of forming the mask layer 138 includes coatingphotoresist, performing the exposure process, and implementing thedevelopment process.

Next, an anisotropic etching operation is performed with use of the masklayer 138 as the mask to remove a portion of the top layer 234 and theinter-layer 232 exposed by the mask layer 138, such that spacers 240 areformed at a sidewall of the transfer transistor 212 and at bothsidewalls of the reset transistor 214, the source follower transistor216, the select transistor 218, and the transistor 220. One of thespacers 240 is constructed by an inner spacer 232 a formed by theinter-layer 232 and an outer spacer 234 a formed by the top layer 234.The anisotropic etching operation is a plasma etching process, forexample. During the etching process, the photodiode doped region 226 iscovered by the mask layer 138, and thus the photodiode doped region 226is not damaged.

Thereafter, as shown in FIG. 5D, the mask layer 138 is removed. Afterthat, the ion implantation process may be performed to form source/draincontact regions 223 in the substrate 200. The source/drain contactregions 223 and the source/drain extension regions 222 together formsource/drain regions 225. Afterwards, an SAB layer 242 is formed on thesubstrate 200, and an inter-layer 232 a and the bottom layer 230 bothexposed by the SAB layer 242 are etched and removed through theanisotropic etching operation, such that predetermined regions in whicha metal silicide layer to be formed are exposed. The material of the SABlayer 242 is, for example, silicon nitride, SiON, or silicon oxide, andthe method of forming the SAB layer 242 includes performing the CVDprocess or an HTO process, for example. In one embodiment, the SAB layer242 covers the photodiode doped region 226, the transfer transistor 212,the floating node doped region 224 and a part of the gate 210 of thereset transistor 214. During the etching process, the spacers 240 of thetransfer transistor 212 and of the reset transistor 214 both covered bythe SAB layer 242 are left. And the spacers 240 of the reset transistor214, of the source follower transistor 216, of the select transistor 218and of the transistor 220 all exposed by the SAB layer 242 are partiallyetched to form spacers 240 a composed of inner spacers 232 b and outerspacers 234 b. A liner layer 230 a sandwiched between one of the spacers240 a and the gates 210 is left after the bottom layer 230 is etched.Next, a salicid process is performed to form a metal silicide layer 244on the gates 210 and on the source/drain regions 225 both exposed by theSAB layer 242. The metal silicide layer 244 is formed by, for example,forming a metal layer on the substrate 200 at first. The metal used forfabricating the metal layer may be a refractory metal selected from oneof the groups consisting of nickel, cobalt, titanium, copper,molybdenum, tantalum, tungsten, erbium, zirconium, platinum and an alloyincluding one or more of said metals. Afterwards, an annealing processis performed to enable the silicon in the substrate 200 or in the gates210 to react with the metal layer and to form a metal silicide having alower resistance. Thereafter, the unreacted metal layer is removed.

Thereafter, the successive processes are performed. Since the subsequentprocesses are well-known to people skilled in the art, detaileddescriptions are omitted herein.

In the above fabrication process, a passivation layer (not shown) may bealternatively formed on a surface of the photodiode doped region 226 soas to prevent current leakage. The passivation layer is, for example, aP-doped region.

Fifth Embodiment

FIGS. 6A through 6D are cross-sectional flow charts schematicallyillustrating a process of fabricating of another MOS device according toan embodiment of the present invention.

Referring to FIG. 6A, a substrate 200 is provided. The substrate 200 is,for example, a semiconductor substrate such as a silicon substrate.First, an isolation structure 202 is formed in the substrate 200 todefine active regions 204 and 206. The active region 204 is a CMOS imagesensor region, and the active region 206 is a non-CMOS image sensorregion. The isolation structure 202 is formed by performing a shallowtrench isolation method or a localized oxidation isolation method. Then,a P-type field region (not shown) is formed at the periphery and on thebottom of the isolation structure 202.

Next, a transfer resistor 212, a reset transistor 214, a source followertransistor 216, a select transistor 218, a floating node doped region224, and a photodiode doped region 226 are formed in the CMOS imagesensor region 204 of the substrate 200. In addition, a transistor 220 isformed in the non-CMOS image sensor region 206. The transfer resistor212, the reset transistor 214, the source follower transistor 216, theselect transistor 218 and the transistor 220 all include gate dielectriclayers 208, gates 210, and source/drain extension regions 222. Thematerial of the gate dielectric layers 208 is, for example, siliconoxide, and the method of forming the gate dielectric layers 208 includesperforming a thermal oxidation process, for example. The material of thegates 210 is polysilicon, for example, and the method of forming thegates 210 includes performing a CVD process, for example. Thesource/drain extension regions 222 may be constructed by performing ionimplantation processes.

Thereafter, a spacer stacked layer 228 is formed on the substrate 200.The spacer stacked layer 228 includes a bottom layer 230, an inter-layer232 and a top layer 234. The etching rate of the inter-layer 232 isdifferent from that of the bottom layer 230 and the top layer 234. Inone embodiment, the materials of the bottom layer 230/the inter-layer232/the top layer 234 include silicon oxide/silicon nitride/siliconoxide, for example, and the thicknesses thereof are 100-300angstrom/100-300 angstrom/300-700 angstrom. The method of forming thebottom layer 230/the inter-layer 232/the top layer 234 includesperforming the CVD process, for example.

After that, referring to FIG. 6B, a mask layer 236 is formed on the toplayer 234. The mask layer 236 has an opening 237 which exposes thephotodiode doped region 226 and is extended to the transfer transistor212 adjacent to the photodiode doped region 226, the floating node dopedregion 224, and a part of the gate 208 of the reset transistor 214. Themask layer 236 is, for example, a patterned photoresist layer, and themethod of forming the mask layer 236 includes coating photoresist,performing an exposure process, and implementing a development process.

After that, the top layer 234 and the inter-layer 232 both exposed bythe opening 237 are removed with use of the mask layer 236 as a hardmask, such that the bottom layer 230 below the inter-layer 232 isexposed. The method of removing the top layer 234 and the inter-layer232 may be a dry etching method or a wet etching method.

Afterwards, referring to FIG. 6C, the mask layer 236 is removed. Anothermask layer 238 is then formed on a region correspondingly exposed by theopening 237, such that the photodiode doped region 226, the transfertransistor 212, the floating node doped region 224 and a part of thegate 208 of the reset transistor 214 are covered while other regions areexposed. The mask layer 238 is, for example, a patterned photoresistlayer, and the method of forming the mask layer 238 includes coatingphotoresist, performing the exposure process, and implementing thedevelopment process.

Next, an anisotropic etching operation is performed with use of the masklayer 238 as the mask to remove a portion of the top layer 234 and theinter-layer 232 exposed by the mask layer 238, such that spacers 240 areformed at a sidewall of the reset transistor 214 and at both sidewallsof the source follower transistor 216, the select transistor 218, andthe transistor 220. each of the spacers 240 is constructed by an innerspacer 232 a formed by the inter-layer 232 and an outer spacer 234 aformed by the top layer 234. The anisotropic etching operation is aplasma etching process, for example. During the etching process, thephotodiode doped region 226 is covered by the mask layer 238, and thus,the photodiode doped region 226 is not damaged through etching.

Thereafter, as shown in FIG. 6D, the mask layer 238 is removed. Afterthat, the ion implantation process may be performed to form source/draincontact regions 223 in the substrate 200. The source/drain contactregions 223 and the source/drain extension regions 222 together formsource/drain regions 225. Afterwards, an SAB layer 242 is formed on thesubstrate 200, and an inter-layer 232 a and the bottom layer 230 bothexposed by the SAB layer 242 are etched and removed through theanisotropic etching operation, such that predetermined regions in whicha metal silicide layer to be formed are exposed. The material of the SABlayer 242 is, for example, silicon nitride, SiON, or silicon oxide, andthe method of forming the SAB layer 242 includes performing the CVDprocess or an HTO process, for example. In one embodiment, the SAB layer242 covers the photodiode doped region 226, the transfer transistor 212,the floating node doped region 224, and a part of the gate 210 of thereset transistor 214. During the etching process, the bottom layer 230covered by the SAB layer 242 is left. And the spacers 240 of the resettransistor 214, of the source follower transistor 216, of the selecttransistor 218 and of the transistor 220 all exposed by the SAB layer242 are partially etched to form spacers 240 a composed of inner spacers232 b and outer spacers 234 b. A liner layer 230 a sandwiched betweenone of the spacers 240 a and the gates 210 is left after the bottomlayer 230 is etched. Next, a salicid process is performed to form ametal silicide layer 244 on the gates 210 and on the source/drainregions 225 both exposed by the SAB layer 242. The metal silicide layer244 is formed by, for example, forming a metal layer on the substrate200 at first. The metal used for fabricating the metal layer may be arefractory metal selected from one of the groups consisting of nickel,cobalt, titanium, copper, molybdenum, tantalum, tungsten, erbium,zirconium, platinum and an alloy including one or more of said metals.Afterwards, an annealing process is performed to enable the silicon inthe substrate 200 or in the gates 210 to react with the metal layer andto form a metal silicide having a lower resistance. Thereafter, theunreacted metal layer is removed.

Thereafter, the successive processes are performed. Since the subsequentprocesses are well-known to people skilled in the art, detaileddescriptions are omitted herein.

In the above fabrication process, a passivation layer (not shown) may bealternatively formed on a surface of the photodiode doped region 226 soas to prevent current leakage. The passivation layer is, for example, aP-doped region.

Six Embodiment

FIGS. 7A through 7D are cross-sectional flow charts schematicallyillustrating a process of fabricating of another MOS device according toan embodiment of the present invention.

Referring to FIG. 7A, a substrate 200 is provided. The substrate 200 is,for example, a semiconductor substrate such as a silicon substrate.First, an isolation structure 202 is formed in the substrate 200 todefine active regions 204 and 206. The active region 204 is a CMOS imagesensor region, and the active region 206 is a non-CMOS image sensorregion. The isolation structure 202 is formed by performing a shallowtrench isolation method or a localized oxidation isolation method. Then,a P-type field region (not shown) is formed at the periphery and on thebottom of the isolation structure 202.

Next, a transfer resistor 212, a reset transistor 214, a source followertransistor 216, a select transistor 218, a floating node doped region224, and a photodiode doped region 226 are formed in the CMOS imagesensor region 204 of the substrate 200. In addition, a transistor 220 isformed in the non-CMOS image sensor region 206. The transfer resistor212, the reset transistor 214, the source follower transistor 216, theselect transistor 218 and the transistor 220 all include gate dielectriclayers 208, gates 210, and source/drain extension regions 222. Thematerial of the gate dielectric layers 208 is, for example, siliconoxide, and the method of forming the gate dielectric layers 208 includesperforming a thermal oxidation process, for example. The material of thegates 210 is polysilicon, for example, and the method of forming thegates 210 includes performing a CVD process, for example. Thesource/drain extension regions 222 may be constructed by performing ionimplantation processes.

Thereafter, a spacer stacked layer 228 is formed on the substrate 200.The spacer stacked layer 228 includes a bottom layer 230, an inter-layer232 and a top layer 234. The etching rate of the inter-layer 232 isdifferent from that of the bottom layer 230 and the top layer 234. Inone embodiment, the materials of the bottom layer 230/the inter-layer232/the top layer 234 include silicon oxide/silicon nitride/siliconoxide, for example, and the thicknesses thereof are 100-300angstrom/100-300 angstrom/300-700 angstrom. The method of forming thebottom layer 230/the inter-layer 232/the top layer 234 includesperforming the CVD process, for example.

After that, referring to FIG. 7B, a mask layer 336 is formed on the toplayer 234. The mask layer 336 has an opening 337 exposing the whole CMOSimage sensor region 204. The mask layer 336 is, for example, a patternedphotoresist layer, and the method of forming the mask layer 336 includescoating photoresist, performing an exposure process, and implementing adevelopment process.

After that, the top layer 234 and the inter-layer 232 both exposed bythe opening 337 are removed with use of the mask layer 336 as a hardmask, such that the bottom layer 230 below the inter-layer 232 isexposed. The method of removing the top layer 234 and the inter-layer232 may be a dry etching method or a wet etching method.

Afterwards, referring to FIG. 7C, the mask layer 336 is removed. Anothermask layer 338 is then formed on a region correspondingly exposed by theopening 337, such that the whole CMOS image sensor region 20 is coveredwhile other regions are exposed. The mask layer 338 is, for example, apatterned photoresist layer, and the method of forming the mask layer338 includes coating photoresist, performing the exposure process, andimplementing the development process.

Next, an anisotropic etching operation is performed with use of the masklayer 338 as the mask to remove a portion of the top layer 234 and theinter-layer 232 exposed by the mask layer 338, such that a liner layer230 a is formed at a sidewall of the resist transistor 214, of thesource follower transistor 216, and of the select transistor 218, andspacers 240 are formed at two sidewalls of the transistor 220. Each ofthe spacers 240 is constructed by an inner spacer 232 a formed by theinter-layer 232 and an outer spacer 234 a formed by the top layer 234.The anisotropic etching operation is a plasma etching process, forexample. During the etching process, the photodiode doped region 226 iscovered by the mask layer 338, and thus the photodiode doped region 226is not damaged.

Thereafter, as shown in FIG. 7D, the mask layer 338 is removed. Afterthat, the ion implantation process may be performed to form source/draincontact regions 223 in the substrate 200. The source/drain contactregions 223 and the source/drain extension regions 222 together formsource/drain regions 225. Afterwards, an SAB layer 242 is formed on thesubstrate 200, and the bottom layer 230 exposed by the SAB layer 242 isetched and removed, such that predetermined regions in which a metalsilicide layer to be formed are exposed. The material of the SAB layer242 is, for example, silicon nitride, SiON, or silicon oxide, and themethod of forming the SAB layer 242 includes performing the CVD processor an HTO process, for example. In one embodiment, the SAB layer 242covers the photodiode doped region 226, the transfer transistor 212, thefloating node doped region 224, and a part of the gate 210 of the resettransistor 214. During the etching process, the bottom layer 230 coveredby the SAB layer 242 is left. The bottom layer 230 exposed by the SABlayer 242 and disposed on the reset transistor 214, the source followertransistor 216, and the select transistor 218 then forms a liner layer230 b at a sidewall of each of the gates 210. The spacers 240 of thetransistor 220 exposed by the SAB layer 242 are partially etched to formspacers 240 a composed of inner spacers 232 b and outer spacers 234 b. Aliner layer 230 a sandwiched between the spacers 240 a and the gates 210is left after the bottom layer 230 is etched. Next, a salicid process isperformed to form a metal silicide layer 244 on the gates 210 and on thesource/drain regions 225 both exposed by the SAB layer 242. The metalsilicide layer 244 is formed by, for example, forming a metal layer onthe substrate 200 at first. The metal used for fabricating the metallayer may be a refractory metal selected from one of the groupsconsisting of nickel, cobalt, titanium, copper, molybdenum, tantalum,tungsten, erbium, zirconium, platinum and an alloy including one or moreof said metals. Afterwards, an annealing process is performed to enablethe silicon in the substrate 200 or in the gates 210 to react with themetal layer and to form a metal silicide having a lower resistance.Thereafter, the unreacted metal layer is removed.

Thereafter, the successive processes are performed. Since the subsequentprocesses are well-known to people skilled in the art, detaileddescriptions are omitted herein.

In the above fabrication process, a passivation layer (not shown) may bealternatively formed on a surface of the photodiode doped region 226 soas to prevent current leakage. The passivation layer is, for example, aP-doped region.

During the etching and the formation of the spacers, the photodiodedoped region is covered by the mask layer. Thus, the photodiode dopedregion is not damaged, and the dark current is not increased. And thebottom layer left on the photodiode region may become the remainedinter-layer or the buffer layer of the anti-reflective layer formed inthe subsequent processes. Due to its thin thickness, the subsequentlyformed anti-reflective layer is extremely close to the photodioderegion, which is conducive to suppression of the reflection.

Although the present invention has been disclosed above by the preferredembodiments, they are not intended to limit the present invention.Anybody skilled in the art can make some modifications and alterationwithout departing from the spirit and scope of the present invention.Therefore, the protecting range of the present invention falls in theappended claims.

1. A method of fabricating a metal oxide semiconductor (MOS) device, comprising: providing a substrate comprising a complementary metal oxide semiconductor (CMOS) image sensor region and a non-CMOS image sensor region; forming a plurality of gates and source/drain regions of transistors on the substrate; forming a photodiode doped region in the CMOS image sensor region; forming a floating node doped region in the CMOS image sensor region; forming a spacer stacked layer covering the gate of each of the transistors on the substrate, the spacer stacked layer at least comprising a bottom layer, an inter-layer, and a top layer from bottom to top; forming a first mask layer on the substrate, the first mask layer having an opening exposing at least the photodiode doped region of the CMOS image sensor region, the opening being extended to a part of the transistor adjacent to the photodiode doped region; performing a removing process to remove the top layer exposed by the opening; removing the first mask layer; forming a second mask layer on a region correspondingly exposed by the opening; removing a portion of the top layer and the inter-layer exposed by the second mask layer so as to form a spacer on a sidewall of each of the transistors; removing the second mask layer; forming a salicide block (SAB) layer on the substrate and removing a portion of the top layer, the inter-layer, and the bottom layer with use of the SAB layer as an etching mask so as to expose a plurality of predetermined regions; and forming a metal silicide layer on each of the predetermined regions.
 2. The method of fabricating the MOS device of claim 1, wherein the materials of the bottom layer/the inter-layer/the top layer comprise silicon oxide/silicon nitride/silicon oxide.
 3. The method of fabricating the MOS device of claim 2, wherein the thicknesses of silicon oxide/silicon nitride/silicon oxide are 300-500 angstrom/100-300 angstrom/300-700 angstrom.
 4. The method of fabricating the MOS device of claim 1, wherein the removing process further comprises removing the inter-layer disposed below the opening.
 5. The method of fabricating the MOS device of claim 4, wherein the materials of the bottom layer/the inter-layer/the top layer comprise silicon oxide/silicon nitride/silicon oxide.
 6. The method of fabricating the MOS device of claim 5, wherein the thicknesses of silicon oxide/silicon nitride/silicon oxide are 100-300 angstrom/100-300 angstrom/300-700 angstrom.
 7. The method of fabricating the MOS device of claim 1, wherein the opening exposes the photodiode doped region, the floating node doped region, the transistor adjacent to the photodiode doped region, and a part of the transistor adjacent to the floating node doped region.
 8. The method of fabricating the MOS device of claim 7, wherein the removing process further comprises removing the inter-layer disposed below the opening.
 9. The method of fabricating the MOS device of claim 1, wherein the opening exposes the whole CMOS image sensor region.
 10. The method of fabricating the MOS device of claim 9, wherein the removing process further comprises removing the inter-layer disposed below the opening.
 11. The method of fabricating the MOS device of claim 1, wherein the first mask layer comprises a patterned photoresist layer.
 12. The method of fabricating the MOS device of claim 1, wherein the second mask layer comprises a patterned photoresist layer.
 13. The method of fabricating the MOS device of claim 1, wherein the material of the SAB layer is selected from one of the groups consisting of silicon nitride, SiON, silicon oxide and a combination thereof.
 14. An MOS device, comprising: a substrate comprising a CMOS image sensor region and a non-CMOS image sensor region; a CMOS image sensor disposed in the CMOS image sensor region, comprising: a photodiode doped region disposed in the substrate; a plurality of first transistors disposed on the substrate, the first transistors comprising a transfer transistor, a reset transistor, a source follower transistor and a select transistor, wherein the transfer transistor is adjacent to the photodiode doped region, and at least a sidewall of a gate of the transfer transistor adjacent to the photodiode doped region comprises no spacers; a floating node doped region disposed in the substrate between the transfer transistor and the reset transistor; at least a bottom layer covering a surface of the transistors having no spacers, a surface of the photodiode doped region, and a surface of the floating node doped region; and an SAB layer covering the bottom layer; and a second transistor disposed in the non-CMOS image sensor region.
 15. The MOS device of claim 14, further comprising an inter-layer at least disposed between the SAB layer and the bottom layer over the photodiode doped region.
 16. The MOS device of claim 15, wherein the material of the inter-layer is different from the material of the bottom layer.
 17. The MOS device of claim 15, wherein the spacers disposed at respective sidewalls of at least one of the first transistors are differently shaped.
 18. The MOS device of claim 17, wherein the first transistor having the differently-shaped spacers at the respective sidewalls is the reset transistor.
 19. The MOS device of claim 17, further comprising a liner layer disposed between the spacers and the first transistors, the spacers comprising an outer spacer and an inner spacer.
 20. The MOS device of claim 19, wherein the material of the outer spacers comprises silicon oxide, while the material of the inner spacers comprises silicon nitride.
 21. The MOS device of claim 15, wherein the inter-layer is disposed between the bottom layer and the SAB layer over the photodiode doped region, the transfer transistor, the floating node doped region and a part of the reset transistor.
 22. The MOS device of claim 21, wherein the spacers of the first transistors and the spacer of the second transistor are equally shaped.
 23. The MOS device of claim 21, wherein the spacer on a sidewall of at least one of the first transistors and the spacer of the second transistor are differently shaped.
 24. The MOS device of claim 15, wherein both sidewalls of the gate of the transfer transistor and a sidewall of the gate of the reset transistor adjacent to the transfer transistor comprise no spacers.
 25. The MOS device of claim 14, wherein the spacers at respective sides of at least one of the first transistors are differently shaped.
 26. The MOS device of claim 25, wherein said first transistor having the differently-shaped spacers at the respective sidewalls is the reset transistor.
 27. The MOS device of claim 25, further comprising a liner layer disposed between the spacers of the first transistors and the gates, the spacers comprising an outer spacer and an inner spacer.
 28. The MOS device of claim 27, wherein the material of the outer spacers comprises silicon oxide, while the material of the inner spacers comprises silicon nitride.
 29. The MOS device of claim 14, wherein the spacers of the first transistors and the spacer of the second transistor are equally shaped.
 30. The MOS device of claim 29, wherein the spacers of the first transistors and the spacer of the second transistor are double-layered spacers, respectively.
 31. The MOS device of claim 14, wherein both sidewalls of the gate of the transfer transistor and a sidewall of the gate of the reset transistor adjacent to the transfer transistor comprise no spacers.
 32. The MOS device of claim 14, wherein all of the first transistors comprise no spacers.
 33. The MOS device of claim 14, further comprising a liner layer disposed on each of the sidewalls of the gates of the first transistors.
 34. The MOS device of claim 14, wherein the material of the bottom layer comprises silicon oxide. 